| 2015 | HPCC | Trio: A Triple Class On-chip Network Design for Efficient Multicore Processors. | Thomas Canhao Xu, Ville Leppnen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
| 2015 | ICA3PP | DBFS: Dual Best-First Search Mapping Algorithm for Shared-Cache Multicore Processors. | Thomas Canhao Xu, Ville Leppnen |
| 2015 | ICSoft | Parallel Applications and On-chip Traffic Distributions: Observation, Implication and Modelling. | Thomas Canhao Xu, Jonne Pohjankukka, Paavo Nevalainen, Ville Leppnen, Tapio Pahikkala |
| 2014 | PDP | Mixed-Criticality Run-Time Task Mapping for NoC-Based Many-Core Systems. | Mohammad Fattah, Amir-Mohammad Rahmani, Thomas Canhao Xu, Anil Kanduri, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
| 2014 | UIC | BDMap: A Heuristic Application Mapping Algorithm for the Big Data Era. | Thomas Canhao Xu, Jussi Toivonen, Tapio Pahikkala, Ville Leppnen |
| 2013 | DASC | DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing. | Thomas Canhao Xu, Ville Leppnen, Martti Forsell |
| 2013 | PACT | OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access. | Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
| 2013 | PPAM | PDNOC: An Efficient Partially Diagonal Network-on-Chip Design. | Thomas Canhao Xu, Ville Leppnen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
| 2012 | HPCC | Implementation and Analysis of Block Dense Matrix Decomposition on Network-on-Chips. | Thomas Canhao Xu, Tapio Pahikkala, Antti Airola, Pasi Liljeberg, Juha Plosila, Tapio Salakoski, Hannu Tenhunen |
| 2012 | MICRO | A high-efficiency low-cost heterogeneous 3D network-on-chip design. | Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
| 2012 | SCOPES | Exploration of heuristic scheduling algorithms for 3D multicore processors. | Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
| 2011 | DDECS | Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip. | Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen |
| 2011 | EuroPar | Study of Hierarchical N-Body Methods for Network-on-Chip Architectures. | Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen |
| 2011 | ICA3PP | A Minimal Average Accessing Time Scheduler for Multicore Processors. | Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen |
| 2010 | DDECS | Tree-model based mapping for energy-efficient and low-latency Network-on-Chip. | Bo Yang, Thomas Canhao Xu, Tero Sntti, Juha Plosila |
| 2010 | EuroPar | A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors. | Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen |
| 2009 | NPC | Explorations of Honeycomb Topologies for Network-on-Chip. | Alexander Wei Yin, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen |