Thomas Edison Yu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2007–2009
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2009 | ASPDAC | Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. | Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara |
| 2007 | VTS | Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. | Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara |