Thomas P. Warwick
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
1
Active years
1999–2008
Best venue rank
A
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | ITC | Measurement Repeatability for RF Test Within the Load-board Constraints of High Density and Fine Pitch SOC Applications. | Thomas P. Warwick, Gustavo Rivera, David Waite, James Russell, Jeffrey Smith |
| 2003 | ITC | Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements. | Thomas P. Warwick |
| 2002 | ITC | What a Device Interface Board Really Costs: An Evaluation of Technical Considerations for Testing Products Operating in the Gigabit Region. | Thomas P. Warwick |
| 1999 | ITC | High speed digital transceivers: A challenge for manufacturing. | Clifford B. Cole, Thomas P. Warwick |
| 1999 | ITC | An accurate simulation model of the ATE test environment for very high speed devices. | Thomas P. Warwick, Jung Cho, Yi Cai, Bill Ortner |