Tohru Adachi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
1982–1988
Best venue rank
A*
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1988 | ITC | Software Environment for 500 MHz VLSI Test System "ULTIMATE". | Tohru Adachi, M. Tanno, Tsuneta Sudo |
| 1982 | DAC | Hierarchical top-down layout design method for VLSI chip. | Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo |