| 2016 | ISCAS | A task allocation method for the DTTR scheme based on task scheduling of fault patterns. | Hiroshi Saito, Masashi Imai, Tomohiro Yoneda |
| 2015 | ICCD | A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. | Tomohiro Yoneda, Masashi Imai |
| 2014 | FMICS | Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. | Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers |
| 2014 | ISCAS | Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. | Masashi Imai, Tomohiro Yoneda |
| 2012 | PRDC | Performance Modeling and Analysis of On-chip Networks for Real-Time Applications. | Masashi Imai, Tomohiro Yoneda |
| 2012 | PRDC | Multi-chip NoCs for Automotive Applications. | Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu |
| 2011 | RTCSA | A Dynamic Link-Width Optimization for Network-on-Chip. | Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano |
| 2010 | ISCAS | A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. | Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Takashi Nanya |
| 2009 | ICCD | N-way ring and square arbiters. | Masashi Imai, Tomohiro Yoneda, Takashi Nanya |
| 2007 | ASPDAC | Symbolic Model Checking of Analog/Mixed-Signal Circuits. | David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda |
| 2006 | ATVA | Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. | Tomohiro Yoneda, Chris J. Myers |
| 2006 | ICCAD | Verification of analog/mixed-signal circuits using labeled hybrid petri nets. | Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda |
| 2004 | ATVA | Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. | Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda |
| 2004 | ATVA | Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. | Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers |
| 2003 | ICCAD | Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. | Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda |
| 2003 | ICCD | Verification of Timed Circuits with Failure Directed Abstractions. | Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda |
| 2002 | CAV | Automatic Derivation of Timing Constraints by Failure Analysis. | Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers |
| 2002 | PRDC | Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. | Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers |
| 2001 | ASPDAC | Conformance and mirroring for timed asychronous circuits. | Bin Zhou, Tomohiro Yoneda, Bernd-Holger Schlingloff |
| 2001 | PRDC | Partial Order Reduction in Verification of Wheel Structured Parameterized Circuits. | Tomoya Kitai, Tomohiro Yoneda |
| 2000 | CAV | VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits. | Tomohiro Yoneda |
| 1996 | FMCAD | BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets. | Tomohiro Yoneda, Hideyuki Hatori, Atsushi Takahara, Shin-ichi Minato |
| 1993 | CAV | Efficient Verification of Parallel Real-Time Systems. | Tomohiro Yoneda, Atsufumi Shibayama, Bernd-Holger Schlingloff, Edmund M. Clarke |