| 2025 | DATE | A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGA. | Kentaroh Katoh, Toru Nakura, Haruo Kobayashi |
| 2025 | ITC | High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops. | Kentaroh Katoh, Toru Nakura, Haruo Kobayashi |
| 2017 | ASPDAC | CMOS-on-quartz pulse generator for low power applications. | Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada |
| 2017 | ASPDAC | A 15 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. | Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada |
| 2017 | ETS | Extension of power supply impedance emulation method on ATE for multiple power domain. | Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada |
| 2016 | DATE | Analytical design optimization of sub-ranging ADC based on stochastic comparator. | Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada |
| 2016 | ITC | Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. | Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada |
| 2015 | DDECS | An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. | Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada |
| 2014 | DDECS | Burst-pulse Generator based on transmission line toward sub-MMW. | Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada |
| 2014 | DDECS | Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. | Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada |
| 2014 | ITC | Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. | Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada |
| 2012 | ITC | Power integrity control of ATE for emulating power supply fluctuations on customer environment. | Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada |
| 2011 | ASPDAC | All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. | Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
| 2011 | DDECS | Decoupling capacitance boosting for on-chip resonant supply noise reduction. | Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada |
| 2010 | ASPDAC | Cascaded time difference amplifier using differential logic delay cell. | Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
| 2010 | DDECS | Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. | Tetsuya Iizuka, Toru Nakura, Kunihiro Asada |
| 2009 | DDECS | Measurement of power supply noise tolerance of self-timed processor. | Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda |
| 2009 | DDECS | All digital baseband 50 Mbps data recovery using 5 oversampling with 0.9 data unit interval clock jitter tolerance. | Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
| 2007 | ASPDAC | Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. | Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada |