Toshihiko Yahara
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
2
Active years
1979–1983
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1983 | DAC | A multiple media delay simulator for MOS LSI circuits. | Kaoru Okazaki, Tomoko Moriya, Toshihiko Yahara |
| 1982 | DAC | A consideration of the number of horizontal grids used in the routing of a masterslice layout. | Masayuki Terai, Hajime Kanada, Koji Sato, Toshihiko Yahara |
| 1981 | DAC | MILD - A cell-based layout system for MOS-LSI. | Koji Sato, Takao Nagai, Mikio Tachibana, Hiroyoshi Shimoyama, Masaru Ozaki, Toshihiko Yahara |
| 1981 | DAC | An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3. | Chiyoji Tanaka, Shinichi Murai, Hiroo Tsuji, Toshihiko Yahara, Kaoru Okazaki, Masayuki Terai, Reiji Katoh, Mikio Tachibana |
| 1981 | ITC | Efficient Logic Verification and Test Validation for MOS LSI Circuits. | Kaoru Okazaki, Toshihiko Yahara |
| 1980 | DAC | A "grid-free" channel router. | Koji Sato, Hiroyoshi Shimoyama, Takao Nagai, Masaru Ozaki, Toshihiko Yahara |
| 1979 | DAC | MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks. | Koji Sato, Takao Nagai, Hiroyoshi Shimoyama, Toshihiko Yahara |