| 2010 | ISCAS | Technology remapping for engineering change with wirelength consideration. | Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh |
| 2008 | ISCAS | Timing-driven X-architecture router among rectangular obstacles. | Hsin-Hsiung Huang, Shu-Ping Chang, Yu-Cheng Lin, Tsai-Ming Hsieh |
| 2008 | ISCAS | Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system. | Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh |
| 2006 | ISCAS | A congestion-driven buffer planner with space reservation. | Hsin-Hsiung Huang, Yung-Ching Chen, Tsai-Ming Hsieh |
| 2005 | ISCAS | Floorplanning with clock tree estimation. | Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh |
| 2005 | ISCAS | A new congestion and crosstalk aware router. | Chin-Hui Wang, Yung-Ching Chen, Tsai-Ming Hsieh, Chih-Hung Lee, Hsin-Hsiung Huang |
| 2004 | DATE | A New Effective Congestion Model in Floorplan Design. | Yi-Lin Hsieh, Tsai-Ming Hsieh |
| 2002 | DATE | A New Formulation for SOC Floorplan Area Minimization Problem. | Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh |
| 2002 | ISCAS | Sequence-pair based placement with boundary constraints. | Chih-Hung Lee, Yi-Lin Hsieh, Hui-Chun Lee, Tsai-Ming Hsieh |
| 2001 | ISCAS | Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. | Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh |
| 2000 | FPGA | Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). | Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh |
| 2000 | ISCAS | Minimum crosstalk channel routing with dogleg. | Kuo-Chih Hsu, Yu-Chung Lin, Po-Xun Chiu, Tsai-Ming Hsieh |