Tsuneta Sudo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
1981–1988
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1988 | ITC | Software Environment for 500 MHz VLSI Test System "ULTIMATE". | Tohru Adachi, M. Tanno, Tsuneta Sudo |
| 1988 | ITC | Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE". | Yoshimitsu Sakagawa, Yusio Akazawa, Naoaki Narumi, Akira Yoshii, Tsuneta Sudo |
| 1988 | ITC | Key Technologies for 500 MHz VLSI Test System "ULTIMATE". | Teruo Tamama, Naoaki Narumi, Tai-ichi Otsuji, Masao Suzuki, Tsuneta Sudo |
| 1982 | DAC | Hierarchical top-down layout design method for VLSI chip. | Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo |
| 1981 | ITC | Analysis and Definition of Overall Timing Accuracy in VLSI Test System. | Shigeru Sugamori, Kenji Yoshida, Hiromi Maruyama, Shinpei Kamata, Tsuneta Sudo |