Tullio Vardanega
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
49
Venues
23
Active years
1991–2024
Best venue rank
A*
Where they publish
- BECRTS7 papers
- BRTCSA4 papers
- CCLOSER3 papers
- CDSD3 papers
- CISORC3 papers
- MulticonferenceSAC3 papers
- ARTSS3 papers
- BICSR3 papers
- BITiCSE2 papers
- ARTAS2 papers
- A*DAC2 papers
- ADATE2 papers
- NationalRTNS2 papers
- AHPDC1 paper
- ASIGCSE1 paper
- ASC1 paper
- AMODELS1 paper
- CETFA1 paper
- BSAFECOMP1 paper
- Journal PublishedEMSOFT1 paper
- CINDIN1 paper
- A*ICSE1 paper
- BLCN1 paper
Papers
49 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | HPDC | A runtime infrastructure for the Continuum of Computing. | Edoardo Tinto, Tullio Vardanega |
| 2024 | ITiCSE | Experimental Analysis of First-Grade Students' Block-Based Programming Problem Solving Processes. | Gabriele Pozzan, Costanza Padova, Chiara Montuori, Barbara Arf, Tullio Vardanega |
| 2023 | SIGCSE | Learning Iteration for Grades 2-3: Puzzles vs. UMC in Code.org. | Enrico Nardelli, Francesco Lacchia, Renzo Davoli, Michael Lodi, Marco Sbaraglia, Veronica Rossano, Enrichetta Gentile, Violetta Lonati, Mattia Monga, Anna Morpurgo, Luca Forlizzi, Giovanna Melideo, Sara Capecchi, Ilenia Fronza, Tullio Vardanega |
| 2023 | SC | A Systematic Mapping Study of Italian Research on Workflows. | Marco Aldinucci, Elena Maria Baralis, Valeria Cardellini, Iacopo Colonnelli, Marco Danelutto, Sergio Decherchi, Giuseppe Di Modica, Luca Ferrucci, Marco Gribaudo, Francesco Iannone, Marco Lapegna, Doriana Medic, Giuseppa Muscianisi, Francesca Righetti, Eva Sciacca, Nicola Tonellotto, Mauro Tortonesi, Paolo Trunfio, Tullio Vardanega |
| 2019 | MODELS | A Little Look Outside of the Box. | Tullio Vardanega |
| 2018 | CLOSER | Designing and Implementing Elastically Scalable Services - A State-of-the-art Technology Review. | Kiyana Bahadori, Tullio Vardanega |
| 2018 | ITiCSE | A two-staged capstone project to foster university-business dialogue. | Tullio Vardanega, Monica Fedeli |
| 2017 | RTAS | EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application. | Enrico Mezzetti, Mikel Fernndez, Alen Bardizbanyan, Irune Agirre, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla |
| 2016 | DSD | PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis. | Francisco J. Cazorla, Jaume Abella, Jan Andersson, Tullio Vardanega, Francis Vatrinet, Iain Bate, Ian Broster, Mikel Azkarate-askasua, Franck Wartel, Liliana Cucu, Fabrice Cros, Glenn Farrall, Adriana Gogonel, Andrea Gianarro, Benoit Triquet, Carles Hernndez, Code Lo, Cristian Maxim, David Morales, Eduardo Quiones, Enrico Mezzetti, Leonidas Kosmidis, Irune Agirre, Mikel Fernndez, Mladen Slijepcevic, Philippa Conmy, Walid Talaboulma |
| 2016 | ETFA | An automated framework for the timing analysis of applications for an automotive multicore processor. | Davide Compagnin, Tullio Vardanega |
| 2016 | SAFECOMP | Automotive Safety Concept Definition for Mixed-Criticality Integration on a COTS Multicore. | Irune Agirre, Mikel Azkarate-askasua, Asier Larrucea, Jon Prez, Tullio Vardanega, Francisco J. Cazorla |
| 2015 | DAC | Increasing confidence on measurement-based contention bounds for real-time round-robin buses. | Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiones, Tullio Vardanega, Francisco J. Cazorla |
| 2015 | DAC | Resource usage templates and signatures for COTS multicore processors. | Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiones, Tullio Vardanega, Francisco J. Cazorla |
| 2015 | DATE | Timing analysis of an avionics case study on complex hardware/software platforms. | Franck Wartel, Leonidas Kosmidis, Adriana Gogonel, Andrea Baldovin, Zo R. Stephenson, Benoit Triquet, Eduardo Quiones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean, Tullio Vardanega, Francisco J. Cazorla |
| 2015 | DSD | IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis. | Irune Agirre, Mikel Azkarate-askasua, Carles Hernndez, Jaume Abella, Jon Prez, Tullio Vardanega, Francisco J. Cazorla |
| 2015 | ECRTS | Experimental Evaluation of Optimal Schedulers Based on Partitioned Proportionate Fairness. | Davide Compagnin, Enrico Mezzetti, Tullio Vardanega |
| 2015 | ISORC | Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors. | Gabriel Fernandez, Jaume Abella, Eduardo Quiones, Luca Fossati, Marco Zulianello, Tullio Vardanega, Francisco J. Cazorla |
| 2015 | SAC | Introduction to partial time composability for COTS multicores. | Gabriel Fernandez, Jaume Abella, Eduardo Quiones, Tullio Vardanega, Luca Fossati, Marco Zulianello, Francisco J. Cazorla |
| 2015 | SAC | A time-composable operating system for the Patmos processor. | Marco Ziccardi, Martin Schoeberl, Tullio Vardanega |
| 2015 | RTSS | EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis. | Marco Ziccardi, Enrico Mezzetti, Tullio Vardanega, Jaume Abella, Francisco J. Cazorla |
| 2014 | DSD | Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture. | Leonidas Kosmidis, Eduardo Quiones, Jaume Abella, Tullio Vardanega, Ian Broster, Francisco J. Cazorla |
| 2014 | ECRTS | Heart of Gold: Making the Improbable Happen to Increase Confidence in MBPTA. | Jaume Abella, Eduardo Quiones, Franck Wartel, Tullio Vardanega, Francisco J. Cazorla |
| 2014 | ECRTS | Putting RUN into Practice: Implementation and Evaluation. | Davide Compagnin, Enrico Mezzetti, Tullio Vardanega |
| 2014 | RTNS | SPRINT: Extending RUN to Schedule Sporadic Tasks. | Andrea Baldovin, Geoffrey Nelissen, Tullio Vardanega, Eduardo Tovar |
| 2014 | RTNS | Supporting Global Resource Sharing in RUN-scheduled Multiprocessor Systems. | Luca Bonato, Enrico Mezzetti, Tullio Vardanega |
| 2013 | EMSOFT | Limited preemptive scheduling of non-independent task sets. | Andrea Baldovin, Enrico Mezzetti, Tullio Vardanega |
| 2013 | INDIN | Supporting industrial use of probabilistic timing analysis with explicit argumentation. | Zo R. Stephenson, Jaume Abella, Tullio Vardanega |
| 2013 | ICSR | Cross-Domain Reuse: Lessons Learned in a Multi-project Trajectory. | Silvia Mazzini, John M. Favaro, Tullio Vardanega |
| 2013 | ICSR | On Software Reference Architectures and Their Application to the Space Domain. | Marco Panunzio, Tullio Vardanega |
| 2013 | ISORC | Achieving timing composability with measurement-based probabilistic timing analysis. | Leonidas Kosmidis, Eduardo Quiones, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla |
| 2013 | SAC | Kernel-level time composability for avionics applications. | Andrea Baldovin, Andrea Graziano, Enrico Mezzetti, Tullio Vardanega |
| 2013 | RTAS | A rapid cache-aware procedure positioning optimization to favor incremental development. | Enrico Mezzetti, Tullio Vardanega |
| 2012 | CLOSER | Towards a New Paas Architecture Generation. | Claudio Guidi, Paolo Anedda, Tullio Vardanega |
| 2012 | ECRTS | Measurement-Based Probabilistic Timing Analysis for Multi-path Programs. | Liliana Cucu-Grosjean, Luca Santinelli, Michael Houston, Code Lo, Tullio Vardanega, Leonidas Kosmidis, Jaume Abella, Enrico Mezzetti, Eduardo Quiones, Francisco J. Cazorla |
| 2011 | CLOSER | Measuring I/O Performance in Xen Paravirtualization Virtual Machines. | Giovanni Giacobbi, Tullio Vardanega |
| 2010 | RTCSA | Towards a Cache-Aware Development of High Integrity Real-Time Systems. | Enrico Mezzetti, Tullio Vardanega |
| 2009 | DATE | An MDE methodology for the development of high-integrity real-time systems. | Silvia Mazzini, Stefano Puri, Tullio Vardanega |
| 2009 | ISORC | Property Preservation and Composition with Guarantees: From ASSERT to CHESS. | Tullio Vardanega |
| 2009 | RTCSA | On Component-Based Development and High-Integrity Real-Time Systems. | Marco Panunzio, Tullio Vardanega |
| 2008 | ECRTS | Fitting Schedulability Analysis Theory into Model-Driven Engineering. | Matteo Bordin, Marco Panunzio, Tullio Vardanega |
| 2007 | RTCSA | An Approach to the Timing Analysis of Hierarchical Systems. | Marco Panunzio, Tullio Vardanega |
| 2006 | ICSR | A UML2 Profile for Reusable and Verifiable Software Components for Real-Time Applications. | Vaclav Cechticky, Martin Egli, Alessandro Pasetti, O. Rohlik, Tullio Vardanega |
| 2006 | RTCSA | Property-Preserving Reuse-Geared Approach to Model-Driven Development. | Tullio Vardanega |
| 2005 | ECRTS | Automated Model-Based Generation of Ravenscar-Compliant Source Code. | Matteo Bordin, Tullio Vardanega |
| 2003 | ECRTS | Issues in Mapping HRT-HOOD to UML. | Silvia Mazzini, Massimo D'Alessandro, Marco Di Natale, Giuseppe Lipari, Tullio Vardanega |
| 1996 | RTSS | Tool support for the construction of statically analysable hard real-time Ada systems. | Tullio Vardanega |
| 1994 | ICSE | Experience with the Development of Hard Real-Time Embedded Ada Software. | Tullio Vardanega |
| 1993 | RTSS | The use of preemptive priority-based scheduling for space applications. | C. M. Bailey, E. Fyfe, Tullio Vardanega, Andy J. Wellings |
| 1991 | LCN | An operating system suited for integrated broadband communications networks. | Tullio Vardanega |