| 1996 | ITC | An ATPG-Based Framework for Verifying Sequential Equivalence. | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Glser |
| 1995 | ASPDAC | Logic optimization by an improved sequential redundancy addition and removal techniques. | Uwe Glser, Kwang-Ting Cheng |
| 1995 | DATE | Gate delay fault test generation for non-scan circuits. | G. Van Brakel, Uwe Glser, Hans G. Kerkhoff, Heinrich Theodor Vierhaus |
| 1995 | VTS | Improving topological ATPG with symbolic techniques. | Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Glser, Heinrich Theodor Vierhaus |
| 1994 | ICCAD | Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation. | Uwe Glser, Heinrich Theodor Vierhaus, M. Kley, A. Wiederhold |
| 1994 | ICCD | Testability Analysis for Test Generation in Synchronous Sequential Circuits. | R. Wolber, Uwe Glser, Heinrich Theodor Vierhaus |
| 1993 | ITC | CMOS Bridges and Resistive Transistor Faults: I | Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Glser |
| 1992 | ITC | Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects. | Uwe Glser, Uwe Hbner, Heinrich Theodor Vierhaus |