| 2014 | VLSID | ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. | Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti |
| 2005 | VLSID | Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits. | Sreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney |
| 2005 | VLSID | Application of Alpha Power Law Models to PLL Design Methodology. | B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni |
| 1999 | ICCD | Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. | Avinash K. Gautam, V. Visvanathan, S. K. Nandy |
| 1999 | VLSID | A New Approach for CMOS Op-Amp Synthesis. | Pradip Mandal, V. Visvanathan |
| 1999 | VLSID | Synthesis of Configurable Architectures for DSP Algorithms. | S. Ramanathan, V. Visvanathan, S. K. Nandy |
| 1997 | VLSID | A Self-Biased High Performance Folded Cascode CMOS Op-Amp. | Pradip Mandal, V. Visvanathan |
| 1997 | VLSID | Low-Power Configurable Processor Array for DLMS Adaptive Filtering. | S. Ramanathan, V. Visvanathan |
| 1996 | VLSID | VLSI Implementation of DSP Architectures. | A. Ratan Gupta, V. Visvanathan |
| 1996 | VLSID | Design of high performance two stage CMOS cascode op-amps with stable biasing. | Pradip Mandal, V. Visvanathan |
| 1996 | VLSID | A systolic architecture for LMS adaptive filtering with minimal adaptation delay. | S. Ramanathan, V. Visvanathan |
| 1995 | VLSID | A modular systolic architecture for delayed least mean squares adaptive filtering. | V. Visvanathan, S. Ramanathan |
| 1994 | VLSID | A CORDIC Based Programmable DXT Processor Array. | V. K. Anuradha, V. Visvanathan |
| 1994 | VLSID | High Speed Digital Filtering on SRAM-Based FPGAs. | Abhijit Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal |
| 1993 | ICCAD | Macromodeling of the A.C. characteristics of CMOS Op-amps. | Pradip Mandal, V. Visvanathan |
| 1993 | ICPP | Supernodal Sparse Cholesky Facotrization on Distributed-Memory Multiprocessors. | Kalluri Eswar, P. Sadayappan, Chua-Huang Huang, V. Visvanathan |
| 1993 | ICPP | A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. | S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan |
| 1993 | VLSID | NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. | Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan |
| 1993 | VLSID | A Methodology for Generating Application Specific Tree Multipliers. | S. Ramanathan, Nibedita Mohanty, V. Visvanathan |
| 1993 | VLSID | A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. | Dinesh Somasekhar, V. Visvanathan |
| 1993 | VLSID | An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. | V. Visvanathan, Nibedita Mohanty, S. Ramanathan |
| 1991 | ICPP | Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors. | Kalluri Eswar, P. Sadayappan, V. Visvanathan |
| 1989 | DAC | A Framework for Scheduling Multi-Rate Circuit Simulation. | Antony P.-C. Ng, V. Visvanathan |
| 1989 | DAC | Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers. | P. Sadayappan, V. Visvanathan |
| 1988 | ICCD | Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization. | P. Sadayappan, V. Visvanathan |
| 1988 | ICS | Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor. | P. Sadayappan, V. Visvanathan |