Vicente Lorente
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
5
Active years
2009–2022
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ICS | Fast-track cache: a huge racetrack memory L1 data cache. | Hugo Trrega, Alejandro Valero, Vicente Lorente, Salvador Petit, Julio Sahuquillo |
| 2014 | HPCC | Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches. | Vicente Lorente, Alejandro Valero, Salvador Petit, Pierfrancesco Foglia, Julio Sahuquillo |
| 2013 | DATE | Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. | Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro Lpez, Jos Duato |
| 2013 | EuroPar | Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity. | Vicente Lorente, Alejandro Valero, Ramon Canal |
| 2012 | EuroPar | Effects of Process Variation on the Access Time in SRAM Cells. | Vicente Lorente, Julio Sahuquillo |
| 2009 | MICRO | An hybrid eDRAM/SRAM macrocell to implement first-level data caches. | Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro Lpez, Jos Duato |