Vladimir Rybalkin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
7
Active years
2015–2021
Best venue rank
B
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | FPL | HALF: Holistic Auto Machine Learning for FPGAs. | Jonas Ney, Dominik Marek Loroch, Vladimir Rybalkin, Nico Weber, Jens Krger, Norbert Wehn |
| 2020 | FPGA | When Massive GPU Parallelism Ain't Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network. | Vladimir Rybalkin, Norbert Wehn |
| 2019 | ISCAS | An In-DRAM Neural Network Processing Engine. | Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn |
| 2018 | DocEng | iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Percentile Based Binarization. | Vladimir Rybalkin, Syed Saqib Bukhari, Muhammad Mohsin Ghaffar, Aqib Ghafoor, Norbert Wehn, Andreas Dengel |
| 2018 | FPL | FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs. | Vladimir Rybalkin, Alessandro Pappalardo, Muhammad Mohsin Ghaffar, Giulio Gambardella, Norbert Wehn, Michaela Blott |
| 2017 | DATE | Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition. | Vladimir Rybalkin, Norbert Wehn, Mohammad Reza Yousefi, Didier Stricker |
| 2016 | VTC | A New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256). | Vladimir Rybalkin, Philipp Schlfer, Norbert Wehn |
| 2015 | PIMRC | A new architecture for high throughput, low latency NB-LDPC check node processing. | Philipp Schlfer, Vladimir Rybalkin, Norbert Wehn, Matthias Alles, Timo Lehnigk-Emden, Emmanuel Boutillon |