| 2025 | DATE | Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators. | Filip Masar, Vojtech Mrazek, Luks Sekanina |
| 2025 | DDECS | Inference Energy Analysis in Context of Hardware-Aware NAS. | Michal Pinos, Jan Klhufek, Vojtech Mrazek, Luks Sekanina |
| 2025 | EUROGP | Multi-objective Evolutionary Design of Explainable EEG Classifier. | Martin Hurta, Anna Ovesna, Vojtech Mrazek, Luks Sekanina |
| 2025 | GECCO | Efficient Scheduling of Transformer Neural Network Computation for Edge-AI Deployment. | David Sedlak, Jan Klhufek, Vojtech Mrazek, Zdenek Vascek |
| 2025 | ICCAD | ApproxGNN: A Pretrained GNN for Parameter Prediction in Design Space Exploration for Approximate Computing. | Ondrej Vlcek, Vojtech Mrazek |
| 2025 | ISCAS | AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs. | Vojtech Mrazek, Zdenek Vascek |
| 2024 | DATE | Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. | Zdenek Vascek, Vojtech Mrazek, Luks Sekanina |
| 2024 | DDECS | Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. | Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina |
| 2024 | ICCAD | Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. | Vojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vascek, Kostas Siozios, Georgios Tzimpragos, Mehdi B. Tahoori, Georgios Zervakis |
| 2024 | IJCNN | ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. | Michal Pinos, Luks Sekanina, Vojtech Mrazek |
| 2023 | DATE | ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. | Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Luks Sekanina |
| 2023 | DDECS | MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. | Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Luks Sekanina |
| 2023 | DDECS | Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial). | Vojtech Mrazek |
| 2023 | DDECS | Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. | Michal Pinos, Vojtech Mrazek, Luks Sekanina |
| 2023 | GECCO | Effective EEG Feature Selection for Interpretable MDD (Major Depressive Disorder) Classification. | Vojtech Mrazek, Soyiba Jawed, Muhammad Arif, Aamir Saeed Malik |
| 2023 | ICANN | Energy Complexity Model for Convolutional Neural Networks. | Jir Sma, Petra Vidnerov, Vojtech Mrazek |
| 2023 | ICCAD | Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. | Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina, Muhammad Shafique |
| 2022 | DDECS | ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. | Jan Klhufek, Vojtech Mrazek |
| 2022 | DSD | Designing Approximate Arithmetic Circuits with Combined Error Constraints. | Milan Ceska, Jir Matys, Vojtech Mrazek, Toms Vojnar |
| 2022 | PPSN | Evolutionary Design of Reduced Precision Preprocessor for Levodopa-Induced Dyskinesia Classifier. | Martin Hurta, Michaela Drahosova, Vojtech Mrazek |
| 2021 | EUROGP | Evolutionary Neural Architecture Search Supporting Approximate Multipliers. | Michal Pinos, Vojtech Mrazek, Luks Sekanina |
| 2020 | DAC | ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. | Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina, Muhammad Shafique |
| 2020 | DATE | ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations. | Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique |
| 2020 | DATE | TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. | Filip Vaverka, Vojtech Mrazek, Zdenek Vascek, Luks Sekanina |
| 2020 | GECCO | Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. | David Hodan, Vojtech Mrazek, Zdenek Vascek |
| 2020 | ICCAD | NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. | Alberto Marchisio, Andrea Massa, Vojtech Mrazek, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique |
| 2020 | SAT | Satisfiability Solving Meets Evolutionary Optimisation in Designing Approximate Circuits. | Milan Ceska, Jir Matys, Vojtech Mrazek, Toms Vojnar |
| 2019 | DAC | autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. | Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vascek, Luks Sekanina, Muhammad Shafique |
| 2019 | DATE | Automated Circuit Approximation Method Driven by Data Distribution. | Zdenek Vascek, Vojtech Mrazek, Luks Sekanina |
| 2019 | ICCAD | ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. | Vojtech Mrazek, Zdenek Vascek, Luks Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique |
| 2018 | CAV | ADAC: Automated Design of Approximate Circuits. | Milan Ceska, Jir Matys, Vojtech Mrazek, Luks Sekanina, Zdenek Vascek, Toms Vojnar |
| 2018 | GECCO | Evolving boolean functions for fast and efficient randomness testing. | Vojtech Mrazek, Marek Ss, Zdenek Vascek, Luks Sekanina, Vashek Matyas |
| 2018 | GECCO | Evolutionary design of large approximate adders optimized for various error criteria. | Vojtech Mrazek, Zdenek Vascek |
| 2017 | DATE | EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. | Vojtech Mrazek, Radek Hrbacek, Zdenek Vascek, Luks Sekanina |
| 2017 | DATE | Towards low power approximate DCT architecture for HEVC standard. | Zdenek Vascek, Vojtech Mrazek, Luks Sekanina |
| 2017 | GECCO | Parallel optimization of transistor level circuits using cartesian genetic programming. | Vojtech Mrazek, Zdenek Vascek |
| 2017 | ICCAD | Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. | Milan Ceska, Jir Matys, Vojtech Mrazek, Luks Sekanina, Zdenek Vascek, Toms Vojnar |
| 2016 | ICCAD | Design of power-efficient approximate multipliers for approximate artificial neural networks. | Vojtech Mrazek, Syed Shakib Sarwar, Luks Sekanina, Zdenek Vascek, Kaushik Roy |
| 2015 | EUC | Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. | Vojtech Mrazek, Zdenek Vascek |
| 2015 | EUROGP | Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. | Vojtech Mrazek, Zdenek Vascek |
| 2015 | GECCO | Evolutionary Approximation of Software for Embedded Systems: Median Function. | Vojtech Mrazek, Zdenek Vascek, Luks Sekanina |