W. Amendola Jr.
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
1995–1995
Best venue rank
National
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1995 | VLSID | A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi |