| 2014 | FPGA | A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only). | Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young |
| 2014 | VLSID | Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. | Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu |
| 2013 | ASPDAC | Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. | Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert |
| 2012 | ASPDAC | ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells. | Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu |
| 2012 | DATE | Almost every wire is removable: A modeling and solution for removing any circuit wire. | Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu |
| 2011 | ASPDAC | On applying erroneous clock gating conditions to further cut down power. | Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu |
| 2007 | DAC | How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs. | Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu |
| 2007 | ISCAS | Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring. | Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu |
| 2005 | ISCAS | FPGA technology mapping optimization by rewiring algorithms. | Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang |