| 2026 | ISCA | Lora: Towards Improved Applicability of Reconfigurable Architecture for Versatile Nonlinear Functions. | Yuan Dai, Guibin Zou, Yuanda Yang, Huan Lin, Jiahang Lou, Yiwen Luo, Xinyu Cai, Wenbo Yin, Wai-Shing Luk, Lingli Wang |
| 2026 | ISCAS | Live Demonstration: An Agile FPGA-Overlayed CGRA SoC for High-Efficiency Computing. | Jiahang Lou, Jianrong Zhang, Yuan Dai, Zewei Zhong, Huan Lin, Wenbo Yin, Lingli Wang |
| 2026 | ISCAS | MOE: An Efficient Multicasting and One-hot Encoding Hybrid Configuration Compression Technique for CGRAs. | Hanyu Zhang, Yuan Dai, Wenbo Yin, Lingli Wang |
| 2026 | ISCAS | FlexEdge: A Hardware-Software Co-Design for Flexible Edge Transformer Inference. | Jiewen Zheng, Zifeng Zhao, Qi Wu, Gengsheng Chen, Wenbo Yin |
| 2025 | ASPDAC | Towards Efficient Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring. | Yuan Dai, Xuchen Gao, Chen Shen, Bingbing Peng, Wenbo Yin, Wai-Shing Luk, Lingli Wang |
| 2025 | DAC | LEMOE: LLM-Enhanced Multi-Objective Bayesian Optimization for Microarchitecture Exploration. | Jingyuan Li, Jianrong Zhang, Ye Li, Wenbo Yin, Lingli Wang |
| 2025 | DAC | Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs. | Jiahang Lou, Qilong Zhu, Yuan Dai, Zewei Zhong, Wenbo Yin, Lingli Wang |
| 2025 | FPL | DEFA: Design Space Exploration for FPGA Overlay Accelerators Through Frequency Prediction and Bayesian Optimization. | Qilong Zhu, Yunfei Dai, Shiyan Bi, Huizhen Kuang, Dylan Wang, Wenbo Yin, Lingli Wang |
| 2025 | ICASSP | ICIMG-Net: Inject Context Information to Motion Generation for Optical Flow Estimation. | Wenbo Yin, Congxuan Zhang, Zhen Chen, Cheng Feng, Liyue Ge, Zige Wang |
| 2025 | ICCAD | DynVec: An End-to-End Framework for Efficient Vector-Dataflow Execution. | Jiangnan Li, Xianfeng Cao, Kaixiang Zhu, Wenbo Yin, Lingli Wang |
| 2024 | ASPDAC | A CGRA Front-end Compiler Enabling Extraction of General Control and Dedicated Operators. | Xuchen Gao, Yunhui Qiu, Yuan Dai, Wenbo Yin, Lingli Wang |
| 2024 | DATE | An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture. | Jiahang Lou, Xuchen Gao, Yiqing Mao, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang |
| 2024 | FPL | CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design. | Yiqing Mao, Xuchen Gao, Jiahang Lou, Yunhui Qiu, Wenbo Yin, Wai-Shing Luk, Lingli Wang |
| 2023 | FCCM | UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization. | Yuan Dai, Yunhui Qiu, Qilong Zhu, Jingyuan Li, Wenbo Yin, Lingli Wang |
| 2023 | FCCM | PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design. | Bingbing Peng, Shaoyang Sun, Yuan Dai, Jingyuan Li, Yunhui Qiu, Kaihang Wang, Wenbo Yin, Lingli Wang |
| 2023 | ISCAS | THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE. | Jingyuan Li, Yunhui Qiu, Guowei Zhu, Qilong Zhu, Wenbo Yin, Lingli Wang |
| 2022 | FPL | TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework. | Yunhui Qiu, Yuhang Cao, Yuan Dai, Wenbo Yin, Lingli Wang |
| 2021 | FPL | A High-performance Open-channel Open-way NAND Flash Controller Architecture. | Yunhui Qiu, Wenbo Yin, Lingli Wang |
| 2019 | FPL | A Low-Latency Multi-Version Key-Value Store Using B-Tree on an FPGA-CPU Platform. | Yuchen Ren, Zhijian Liao, Xiaozhong Shi, Jinyu Xie, Yunhui Qiu, Hankun Lv, Wenbo Yin, Lingli Wang, Bowei Yu, Hua Chen, Xianjun He |
| 2018 | ISCAS | Ultra-Low Latency and High Throughput Key-Value Store Systems Over Ethernet. | Li Ding, Wenbo Yin, Lingli Wang |
| 2017 | FPL | FPGA acceleration of the scoring process of X!TANDEM for protein identification. | Jin Qiu, Ping Kang, Li Ding, Yipeng Yuan, Wenbo Yin, Lingli Wang |
| 2016 | FPL | Memory efficient and high performance key-value store on FPGA using Cuckoo hashing. | Wei Liang, Wenbo Yin, Ping Kang, Lingli Wang |