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Wim Heirman

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

26

Venues

14

Active years

2006–2026

Best venue rank

A*

Where they publish

Papers

26 indexed papers, newest first.

YearVenueTitleAuthors
2026ISCAATX: Accelerator Task Extensions.Gerasimos Gerogiannis, Stijn Eyerman, Josep Torrellas, Wim Heirman
2025ISPASSMulti-Core Aware Evaluation of Prefetchers.Mart Torrents, Paul Caheny, Stijn Eyerman, Wim Heirman
2025ISPASSMeasuring Performance Overheads of Software Memory Management Using Functional-First Simulators.Yves Vandriessche, Wim Heirman, Ed Nutting, Jeremy Birch, Judah Daniels, Mae Hood, Pascal Costanza
2025MICRODECA: A Near-Core LLM Decompression Accelerator Grounded on a 3D Roofline Model.Gerasimos Gerogiannis, Stijn Eyerman, Evangelos Georganas, Wim Heirman, Josep Torrellas
2024ISPASSMessage from the Program Chairs; ISPASS 2024.Wim Heirman, Stijn Eyerman
2023ISPASSSimulating Wrong-Path Instructions in Decoupled Functional-First Simulation.Stijn Eyerman, Sam Van den Steen, Wim Heirman, Ibrahim Hur
2022HPCALoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications.Alen Sabu, Harish Patil, Wim Heirman, Trevor E. Carlson
2022ISPASSDRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks.Stijn Eyerman, Wim Heirman, Ibrahim Hur
2022ISPASSScale-Model Architectural Simulation.Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout
2021CGOELFies: Executable Region Checkpoints for Performance Analysis and Simulation.Harish Patil, Alexander Isaev, Wim Heirman, Alen Sabu, Ali Hajiabadi, Trevor E. Carlson
2021MICROEnabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions.Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur
2018ISPASSExtending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks.Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
2018SCMany-core graph workload analysis.Stijn Eyerman, Wim Heirman, Kristof Du Bois, Joshua B. Fryman, Ibrahim Hur
2015ISCAThe load slice core microarchitecture.Trevor E. Carlson, Wim Heirman, Osman Allam, Stefanos Kaxiras, Lieven Eeckhout
2014HPCAUndersubscribed threading on clustered cache architectures.Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout
2014ICSAutomatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor.Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout
2014ISPASSBarrierPoint: Sampled simulation of multi-threaded applications.Trevor E. Carlson, Wim Heirman, Kenzo Van Craeynest, Lieven Eeckhout
2013ISPASSSampled simulation of multi-threaded applications.Trevor E. Carlson, Wim Heirman, Lieven Eeckhout
2013PDPMaking Communication a First-Class Citizen in Multicore Partitioning.Poona Bahrebar, Ruxandra-Marina Florea, Wim Heirman, Leon Denis, Adrian Munteanu, Dirk Stroobandt
2012ICA3PPThe Impact of Global Communication Latency at Extreme Scales on Krylov Methods.Thomas J. Ashby, Pieter Ghysels, Wim Heirman, Wim Vanroose
2011EuroParEvaluating Application Vulnerability to Soft Errors in Multi-level Cache Hierarchy.Zhe Ma, Trevor E. Carlson, Wim Heirman, Lieven Eeckhout
2011SCSniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation.Trevor E. Carlson, Wim Heirman, Lieven Eeckhout
2010ICPADSPinComm: Characterizing Intra-application Communication for the Many-Core Era.Wim Heirman, Dirk Stroobandt, Narasinga Rao Miniskar, Roel Wuyts, Francky Catthoor
2010RSPPerformance evaluation for passive-type Optical network-on-chip.Atef Allam, Ian O'Connor, Wim Heirman
2009HOTILow-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects.Iigo Artundo, Wim Heirman, Mikel Loperena, Christof Debaes, Jan M. Van Campenhout, Hugo Thienpont
2006ISPAReconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior.Iigo Artundo, Daniel Manjarres, Wim Heirman, Christof Debaes, Joni Dambre, Jan M. Van Campenhout, Hugo Thienpont