| 2026 | DATE | SMIX: Schedulable Instruction Set Architecture Extension Interface for Multi-Operand Operators. | Shufan He, Hanmo Wang, Kefa Chen, Xuyin Chen, Xianhua Liu, Chun Yang |
| 2025 | ICCAD | Software-Style Hardware Debugging: A Hardware Generation, Simulation and Debugging Framework. | Weiran Liu, Shixuan Chen, Chun Yang, Xianhua Liu |
| 2024 | ICCD | Multi: Reduce Energy Overhead of Criticality-Aware Dynamic Instruction Scheduling for Energy Efficiency. | Honglan Zhan, Chenxi Wang, Xin Wang, Chun Yang, Xianhua Liu, Xu Cheng |
| 2023 | DATE | A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation. | Hongwei Cui, Shuhao Liang, Yujie Cui, Weiqi Zhang, Honglan Zhan, Chun Yang, Xianhua Liu, Xu Cheng |
| 2023 | DATE | High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation. | Honglan Zhan, Chenxi Wang, Hongwei Cui, Xianhua Liu, Feng Liu, Xu Cheng |
| 2020 | IPCCC | Efficient arithmetic expression optimization with weighted adjoint matrix. | Xianhua Liu, Chun Yang, Zixin Guan |
| 2020 | TrustCom | FTCLNet: Convolutional LSTM with Fourier Transform for Vulnerability Detection. | Defu Cao, Jing Huang, Xuanyu Zhang, Xianhua Liu |
| 2017 | VEE | Content Look-Aside Buffer for Redundancy-Free Virtual Disk I/O and Caching. | Chun Yang, Xianhua Liu, Xu Cheng |
| 2016 | ICCD | MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications. | Yan Sui, Chun Yang, Dong Tong, Xianhua Liu, Xu Cheng |
| 2015 | ICA3PP | Exploration of the Relationship Between Just-in-Time Compilation Policy and Number of Cores. | Mingkai Huang, Xianhua Liu, Tingyu Zhang, Xu Cheng |
| 2015 | ICPP | An Energy-Efficient Branch Prediction with Grouped Global History. | Mingkai Huang, Dan He, Xianhua Liu, Mingxing Tan, Xu Cheng |
| 2012 | DATE | Energy-efficient branch prediction with Compiler-guided History Stack. | Mingxing Tan, Xianhua Liu, Zichao Xie, Dong Tong, Xu Cheng |
| 2012 | ICS | CVP: an energy-efficient indirect branch prediction with compiler-guided value pattern. | Mingxing Tan, Xianhua Liu, Tong Tong, Xu Cheng |
| 2010 | FPGA | Bit-level optimization for high-level synthesis and FPGA-based acceleration. | Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong |
| 2007 | SAC | Efficient code size reduction without performance loss. | Xianhua Liu, Jiyu Zhang, Xu Cheng |