| 2025 | DAC | Finding the Pareto Frontier of Low-Precision Data Formats and MAC Architecture for LLM Inference. | Brian Crafton, Xiaochen Peng, Xiaoyu Sun, Ashwin Sanjay Lele, Bo Zhang, Win-San Khwa, Kerem Akarvardar |
| 2024 | ICCAD | Non-volatile Memory Technologies for Edge AI Applications. | Xiaoyu Sun, Win-San Khwa, Xiaochen Peng, Meng-Fan Chang, Kerem Akarvardar |
| 2021 | DATE | A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. | Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu |
| 2021 | ISCAS | Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. | Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu |
| 2021 | ISCAS | Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator. | Panni Wang, Xiaochen Peng, Wriddhi Chakraborty, Asif Khan, Suman Datta, Shimeng Yu |
| 2020 | DAC | A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. | Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu |
| 2020 | DATE | Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. | Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu |
| 2020 | ICCAD | XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. | Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu |
| 2020 | ISCAS | MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture. | Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu |
| 2020 | ISCAS | A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out. | Yandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Mark S. Rodder, Jae-Sun Seo, Shimeng Yu |
| 2019 | DAC | Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. | Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian |
| 2019 | ISCAS | Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture. | Xiaochen Peng, Rui Liu, Shimeng Yu |
| 2018 | ASPDAC | Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. | Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu |
| 2018 | DAC | Parallelizing SRAM arrays with customized bit-cell for binary neural networks. | Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu |
| 2018 | DATE | XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. | Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu |
| 2018 | ISCAS | Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing. | Jiyong Woo, Xiaochen Peng, Shimeng Yu |