Xin-Wei Shih
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
4
Active years
2010–2014
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | ISLPED | Buffered clock tree synthesis considering self-heating effects. | Chung-Wei Lin, Tzu-Hsuan Hsu, Xin-Wei Shih, Yao-Wen Chang |
| 2013 | ASPDAC | Layer minimization in escape routing for staggered-pin-array PCBs. | Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng |
| 2013 | ASPDAC | Symmetrical buffered clock-tree synthesis with supply-voltage alignment. | Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao |
| 2012 | ASPDAC | Clock rescheduling for timing engineering change orders. | Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang |
| 2010 | ASPDAC | Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. | Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang |
| 2010 | DAC | Fast timing-model independent buffered clock-tree synthesis. | Xin-Wei Shih, Yao-Wen Chang |
| 2010 | ICCAD | High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. | Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang |