| 2013 | ETS | A mutual characterization based SAR ADC self-testing technique. | H.-J. Lin, Xuan-Lun Huang, Jiun-Lang Huang |
| 2013 | ICCAD | An IDDQ-based source driver IC design-for-test technique. | S.-S. Lin, C.-L. Kao, Jiun-Lang Huang, C.-C. Lee, Xuan-Lun Huang |
| 2011 | ASPDAC | A self-testing and calibration method for embedded successive approximation register ADC. | Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu |
| 2011 | ETS | A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. | Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai |
| 2010 | DATE | A robust ADC code hit counting technique. | Jiun-Lang Huang, Kuo-Yu Chou, Ming-Huan Lu, Xuan-Lun Huang |
| 2010 | VTS | An ADC/DAC loopback testing methodology by DAC output offsetting and scaling. | Xuan-Lun Huang, Jiun-Lang Huang |
| 2009 | ASPDAC | Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. | Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang |
| 2006 | ASPDAC | A routability constrained scan chain ordering technique for test power reduction. | Xuan-Lun Huang, Jiun-Lang Huang |