Y. Y. H. Lam
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
1994–1997
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1997 | FPL | FPGA implementation of a digital IQ demodulator using VHDL. | Ching-Chuen Jong, Y. Y. H. Lam, L. S. Ng |
| 1994 | ISCAS | Time-Zone: A New Algorithm for Register Allocation in Data Path Synthesis. | Ching-Chuen Jong, Y. Y. H. Lam, S. S. Lim, T. S. Teng |