| 2023 | ISPASS | LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators. | Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2023 | MICRO | HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. | Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2023 | MICRO | Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. | Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze |
| 2022 | MICRO | Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. | Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2021 | ISPASS | Architecture-Level Energy Estimation for Heterogeneous Computing Systems. | Francis Wang, Yannan Nellie Wu, Matthew E. Woicik, Joel S. Emer, Vivienne Sze |
| 2021 | ISPASS | Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. | Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer |
| 2020 | ISPASS | An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs. | Yannan Nellie Wu, Vivienne Sze, Joel S. Emer |
| 2019 | ICCAD | Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs. | Yannan Nellie Wu, Joel S. Emer, Vivienne Sze |