| 2026 | DATE | MGPA: A Memristor-based Genome Processing Accelerator for Single-cell RNA Sequencing. | Yang Han, Lianfeng Yu, Teng Zhang, Bowen Wang, Yihang Zhu, Lei Cai, Yaoyu Tao, Yuchao Yang |
| 2025 | HPCA | PROCA: Programmable Probabilistic Processing Unit Architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference. | Yihan Fu, Anjunyi Fan, Wenshuo Yue, Hongxiao Zhao, Daijing Shi, Qiuping Wu, Jiayi Li, Xiangyu Zhang, Yaoyu Tao, Yuchao Yang, Bonan Yan |
| 2025 | ICCD | ASMA: An Anisotropy Scaling Memristor-Based Accelerator for LLM Inference. | Zijian Xiong, Xiangrui Yang, Yuhang Zhang, Yue Zhou, Jianguo Yang, Yaoyu Tao, Xiangshui Miao, Yuhui He |
| 2024 | MICRO | MeMCISA: Memristor-Enabled Memory-Centric Instruction-Set Architecture for Database Workloads. | Yihang Zhu, Lei Cai, Lianfeng Yu, Anjunyi Fan, Longhao Yan, Zhaokun Jing, Bonan Yan, Pek Jun Tiw, Yuqi Li, Yaoyu Tao, Yuchao Yang |
| 2023 | FPGA | Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search. | Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yaoyu Tao, Yuchao Yang |
| 2023 | HPCA | eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs. | Junkang Zhu, Yaoyu Tao, Zhengya Zhang |
| 2022 | ISCAS | High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder. | Yaoyu Tao, Cedric Choi |
| 2022 | ISCAS | Fast and Scalable Memristive In-Memory Sorting with Column-Skipping Algorithm. | Lianfeng Yu, Zhaokun Jing, Yuchao Yang, Yaoyu Tao |
| 2021 | GLOBECOM | DNC-Aided SCL-Flip Decoding of Polar Codes. | Yaoyu Tao, Zhengya Zhang |
| 2021 | MICRO | HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer. | Yaoyu Tao, Zhengya Zhang |
| 2019 | ISCAS | An Automated FPGA-Based Framework for Rapid Prototyping of Nonbinary LDPC Codes. | Yaoyu Tao, Qi Wu |
| 2013 | ISCAS | Efficient in situ error detection enabling diverse path coverage. | Chia-Hsiang Chen, Yaoyu Tao, Zhengya Zhang |
| 2012 | ISCAS | High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders. | Yaoyu Tao, Youn Sung Park, Zhengya Zhang |