Yaru Yan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2011–2011
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | FPGA | A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). | Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan |