Yaun-Chung Hsu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
1993–2008
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | FPL | A technique for minimizing power during FPGA placement. | Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-Chung Hsu, Arun Kundu, Andrew A. Kennings |
| 1998 | ICCD | Timing analysis of combinational circuits containing complex gates. | Yaun-Chung Hsu, Hsi-Chuan Chen, Shangzhi Sun, David Hung-Chang Du |
| 1998 | ICCD | Finding the longest simple path in cyclic combinational circuits. | Yaun-Chung Hsu, Shangzhi Sun, David Hung-Chang Du |
| 1994 | ICCD | On Valid Clocking for Combinational Circuits. | Shangzhi Sun, David Hung-Chang Du, Yaun-Chung Hsu, Hsi-Chuan Chen |
| 1993 | ICCD | A Path Sensitization Approach to Area Reduction. | Hsi-Chuan Chen, Siu-Wing Cheng, Yaun-Chung Hsu, David Hung-Chang Du |