| 2024 | WACV | Deep Plug-and-play Nighttime Non-blind Deblurring with Saturated Pixel Handling Schemes. | Hung-Yu Shu, Yi-Hsien Lin, Yi-Chang Lu |
| 2022 | ICASSP | CF-Net: Complementary Fusion Network for Rotation Invariant Point Cloud Completion. | Bo-Fan Chen, Yang-Ming Yeh, Yi-Chang Lu |
| 2022 | ISCAS | An Alignment-Based Hardware Accelerator for Rapid Prediction of RNA Secondary Structures. | Shih-Shiuan Weng, Yang-Ming Yeh, Yu-Cheng Li, Yi-Chang Lu |
| 2021 | DATE | Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. | Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, Charlie Chung-Ping Chen |
| 2021 | ISCAS | A Memory-Efficient Accelerator for DNA Sequence Alignment with Two-Piece Affine Gap Tracebacks. | Jing-Ping Wu, Yi-Chien Lin, Ying-Wei Wu, Shih-Wei Hsieh, Ching-Hsuan Tai, Yi-Chang Lu |
| 2021 | VCIP | Using Regularity Unit As Guidance For Summarization-Based Image Resizing. | Fang-Tsung Hsiao, Yi-Hsien Lin, Yi-Chang Lu |
| 2020 | BIBE | Comprehensive Study of Keywords for Sequence-Based Automatic Annotation of Protein Functions. | Yu-Cheng Li, Mao-Jan Lin, Xiao-Xuan Huang, Chien-Yu Chen, Yi-Chang Lu |
| 2020 | ISCAS | An Image Deblurring Processor for Chromatic Aberration Based on the Primal-Dual Algorithm with Cross-Channel Prior. | Chia-Han Huang, Yi-Chang Lu |
| 2020 | VCIP | HDR Deghosting Using Motion-Registration-Free Fusion in the Luminance Gradient Domain. | Cheng-Yeh Liou, Cheng-Yen Chuang, Chia-Han Huang, Yi-Chang Lu |
| 2019 | BIBE | Banded Pair-HMM Algorithm for DNA Variant Calling and Its Hardware Accelerator Design. | Ming-Hung Chen, Mao-Jan Lin, Yu-Cheng Li, Yi-Chang Lu |
| 2019 | ISCAS | A Special-Purpose Processor for FFT-Based Digital Refocusing using 4-D Light Field Data. | Man-Rong Chen, Hao-Wei Liu, Yi-Hsien Lin, Yi-Chang Lu |
| 2018 | ICIP | Subpixel-Level-Accurate Algorithm for Removing Double-Layered Reflections from a Single Image. | Shih-Wei Hsieh, Yao-Cheng Yang, Chi-Ming Yeh, Sheng-Jui Huang, Yi-Chang Lu |
| 2018 | ISCAS | A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs. | Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu |
| 2018 | ISCAS | A High Dynamic Range Light Field Camera and Its Built-In Data Processor Design. | Po-Hsiang Hsu, Yang-Ming Yeh, Chi-Ming Yeh, Yi-Chang Lu |
| 2018 | ISCAS | A Hybrid Flow for Multiple Sequence Alignment with a BLASTn Based Pairwise Alignment Processor. | Mao-Jan Lin, Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu |
| 2017 | CVPR | Deep Co-occurrence Feature Learning for Visual Object Recognition. | Ya-Fang Shih, Yang-Ming Yeh, Yen-Yu Lin, Ming-Fang Weng, Yi-Chang Lu, Yung-Yu Chuang |
| 2014 | ISCAS | A pixel-based depth estimation algorithm and its hardware implementation for 4-D light field data. | Che-Wei Chang, Man-Rong Chen, Po-Hsiang Hsu, Yi-Chang Lu |
| 2013 | ASPDAC | Power distribution network modeling for 3-D ICs with TSV arrays. | Chi-Kai Shen, Yi-Chang Lu, Yih-Peng Chiou, Tai-Yu Cheng, Tzong-Lin Wu |
| 2013 | ICASSP | Parallel architecture and hardware implementation of pre-processor and post-processor for sequence assembly. | Yuan-Hsiang Kuo, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu |
| 2013 | ISLPED | Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. | Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu |
| 2010 | ASPDAC | A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects. | Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu |
| 2010 | ICASSP | Light field based digital refocusing using a DSLR camera with a pinhole array mask. | Chih-Chieh Chen, Yi-Chang Lu, Ming-Shing Su |
| 2010 | ICIP | Depth estimation of light field data from pinhole-masked DSLR cameras. | Chih-Chieh Chen, Shih-Chieh Fan Chiang, Xiao-Xuan Huang, Ming-Shing Su, Yi-Chang Lu |
| 2009 | ICCAD | Thermal modeling for 3D-ICs with integrated microchannel cooling. | Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu |
| 2008 | ICCAD | A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects. | Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, Philip C. W. Ng |
| 2006 | FPGA | Performance benefits of monolithically stacked 3D-FPGA. | Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong |
| 2001 | DAC | Min/max On-Chip Inductance Models and Delay Metrics. | Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi |