Yi Diao
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2012–2016
Best venue rank
B
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ASPDAC | Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). | Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu |
| 2016 | ASPDAC | To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO. | Xing Wei, Yi Diao, Yu-Liang Wu |
| 2015 | DATE | A coupling area reduction technique applying ODC shifting. | Yi Diao, Tak-Kei Lam, Xing Wei, Yu-Liang Wu |
| 2015 | DATE | A universal macro block mapping scheme for arithmetic circuits. | Xing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu |
| 2014 | VLSID | Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. | Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu |
| 2012 | ASPDAC | ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells. | Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu |