| 2025 | DAC | Reinforcement Learning-Driven Window Selection for Enhanced Window-Based Rip-up and Reroute in Chip Detailed Routing. | Yu-Chan Keng, Yu-Chun Pai, Wen-Hao Liu, Haoxing Ren, Danny Liu, Rongjian Liang, Mark Ho, Anthony Agnesina, Yih-Lang Li |
| 2025 | DAC | Synthesis of CFET Cell Library Leveraging Backside Metal Routing. | Ting-Xin Lin, Yih-Lang Li |
| 2024 | DAC | Arbitrary-size Multi-layer OARSMT RL Router Trained with Combinatorial Monte-Carlo Tree Search. | Liang-Ting Chen, Hung-Ru Kuo, Yih-Lang Li, Mango C.-T. Chao |
| 2021 | DAC | A Complete PCB Routing Methodology with Concurrent Hierarchical Routing. | Shih-Ting Lin, Hung-Hsiao Wang, Chia-Yu Kuo, Yolo Chen, Yih-Lang Li |
| 2021 | ICCAD | DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. | Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo |
| 2020 | APNOMS | Smart Self-Checkout Carts Based on Deep Learning for Shopping Activity Recognition. | Hong-Chuan Chi, Muhammad Atif Sarwar, Yousef-Awwad Daraghmi, Kuan-Wen Liu, Ts-U Ik, Yih-Lang Li |
| 2020 | ICCAD | DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. | Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo |
| 2020 | ICCAD | /TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis. | Tai-Cheng Lee, Cheng-Yen Yang, Yih-Lang Li |
| 2020 | ICCAD | MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. | Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera |
| 2020 | WCNC | Smart Shopping Carts Based on Mobile Computing and Deep Learning Cloud Services. | Muhammad Atif Sarwar, Yousef-Awwad Daraghmi, Kuan-Wen Liu, Hong-Chuan Chi, Ts-U Ik, Yih-Lang Li |
| 2019 | DAC | NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. | Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera |
| 2019 | ICCAD | DATC RDF-2019: Towards a Complete Academic Reference Design Flow. | Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo |
| 2018 | DATE | LESAR: A dynamic line-end spacing aware detailed router. | Ying-Chi Wei, Radhamanjari Samanta, Yih-Lang Li |
| 2018 | ICCAD | DATC RDF: an academic flow from logic synthesis to detailed routing. | Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam |
| 2017 | ICCAD | DATC RDF: Robust design flow database: Invited paper. | Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, Gi-Joon Nam |
| 2016 | ICCAD | OpenDesign flow database: the infrastructure for VLSI design and design automation research. | Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, Yih-Lang Li |
| 2015 | DATE | SubHunter: a high-performance and scalable sub-circuit recognition method with Prfer-encoding. | Hong-Yan Su, Chih-Hao Hsu, Yih-Lang Li |
| 2014 | DAC | Density-aware Detailed Placement with Instant Legalization. | Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang |
| 2014 | ICCAD | Fast and accurate emissivity and absolute temperature maps measurement for integrated circuits. | Hsueh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Yiyu Shi, Shu-Fei Tsai |
| 2013 | DAC | Optimization of placement solutions for routability. | Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li |
| 2013 | DAC | Routing congestion estimation with real design constraints. | Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan |
| 2012 | ASPDAC | Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization. | Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li |
| 2012 | ICCAD | Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. | Iris Hui-Ru Jiang, Zhuo Li, Yih-Lang Li |
| 2012 | ICCAD | TRIAD: A triple patterning lithography aware detailed router. | Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li |
| 2012 | ICCAD | A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. | Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh |
| 2011 | ASPDAC | Negotiation-based layer assignment for via count and via overflow minimization. | Wen-Hao Liu, Yih-Lang Li |
| 2011 | ICCAD | Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. | Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li |
| 2011 | ICCAD | High-quality global routing for multiple dynamic supply voltage designs. | Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao |
| 2010 | ASPDAC | Dead via minimization by simultaneous routing and redundant via insertion. | Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li |
| 2010 | ASPDAC | Minimizing clock latency range in robust clock tree synthesis. | Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen |
| 2010 | DAC | Double patterning lithography aware gridless detailed routing with innovative conflict graph. | Yen-Hung Lin, Yih-Lang Li |
| 2010 | DAC | Multi-threaded collision-aware global routing with bounded-length maze routing. | Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao |
| 2009 | ASPDAC | Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing. | Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li |
| 2009 | ICCAD | GRPlacer: Improving routability and wire-length of global routing with circuit replacement. | Ke-Ren Dai, Chien-Hung Lu, Yih-Lang Li |
| 2009 | ICCD | Topology-driven cell layout migration with collinear constraints. | De-Shiun Fu, Ying-Zhih Chaung, Yen-Hung Lin, Yih-Lang Li |
| 2007 | ICCS | A Simulation-Based Hybrid Optimization Technique for Low Noise Amplifier Design Automation. | Yiming Li, Shao-Ming Yu, Yih-Lang Li |