| 2012 | ISCAS | Efficient TWIN-VQ audio decoder implementation on a configurable processor using instruction extension. | Yin-Tsung Hwang, Tao-Hsing Huang |
| 2012 | ISCAS | An efficient QR decomposition design for MIMO systems. | Jing-Shiun Lin, Yin-Tsung Hwang, Po-Han Chu, Ming-Der Shieh, Shih-Hao Fang |
| 2012 | ISCAS | Low power 10-transistor full adder design based on degenerate pass transistor logic. | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
| 2011 | ISCAS | Low complexity baseband transceiver design for narrow band power line communication. | Yin-Tsung Hwang, Feng-Ming Chang, Shin-Wen Chen |
| 2010 | ISCAS | MMSE-QR factorization systolic array design for applications in MIMO signal detections. | Yin-Tsung Hwang, Wei-Da Chen |
| 2008 | ISCAS | A low complexity complex QR factorization design for signal detection in MIMO OFDM systems. | Yin-Tsung Hwang, Wei-Da Chen |
| 2006 | ISCAS | A high speed and energy efficient full adder design using complementary & level restoring carry logic. | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho |
| 2005 | ISCAS | Block-wise adaptive modulation for OFDM WLAN systems. | Yin-Tsung Hwang, Chen-Yu Tsai, Cheng-Chen Lin |
| 2004 | ISCAS | VLSI architecture exploration for sliding-window Log-MAP decoders. | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo |
| 2003 | ISCAS | FPGA realization of an OFDM frame synchronization design for dispersive channels. | Yin-Tsung Hwang, Kuo-Wei Liao, Chien-Hsing Wu |
| 2002 | ISCAS | An area-efficient systolic division circuit over GF(2 | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang |
| 2001 | ISCAS | Design and implementation of channel equalizers for block transmission systems. | Yin-Tsung Hwang, Jih-Cheng Han, Jing-Yi Liu |
| 2001 | ISCAS | Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang |
| 1996 | ICPADS | Distributed arithmetic-based architectures for high speed IIR filter design. | Ching-Long Su, Yin-Tsung Hwang |