| 2017 | ISCAS | A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction. | Gyunam Jeon, Yong-Bin Kim |
| 2011 | ICCD | Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset. | Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi |
| 2009 | VTS | Soft-Error Hardening Designs of Nanoscale CMOS Latches. | Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi |
| 2007 | ISCAS | Optimal Body Biasing for Minimum Leakage Power in Standby Mode. | Kyung Ki Kim, Yong-Bin Kim |
| 2007 | ISCAS | A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control. | Yong-Bin Kim, Kyung Ki Kim, James T. Doyle |
| 2005 | ISCAS | QCA-based nano circuits design [adder design example]. | Rui Tang, Fengming Zhang, Yong-Bin Kim |
| 2004 | ISCAS | A fast and precise interconnect capacitive coupling noise model. | Young-Jun Lee, Yong-Bin Kim |
| 2004 | ISCAS | Low power real time electronic neuron VLSI design using subthreshold technique. | Young-Jun Lee, Jihyun Lee, Yong-Bin Kim, Joseph Ayers, Alexander Volkovskii, Allen I. Selverston, Henry D. I. Abarbanel, Mikhail I. Rabinovich |
| 2003 | NCA | Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. | Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi |
| 2002 | ISCAS | Design flow of robust routed power distribution for low power ASIC. | Dae Woon Kang, Yong-Bin Kim |
| 2002 | PRDC | Hardware/Software Co-Reliability of Configurable Digital Systems. | Minsu Choi, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi |
| 1997 | ASPDAC | A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps. | Yong-Bin Kim, Tom Chen |