| 2013 | IOLTS | A failure triage engine based on error trace signature extraction. | Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris |
| 2012 | ASPDAC | Automated data analysis techniques for a modern silicon debug environment. | Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita |
| 2012 | DATE | Leveraging reconfigurability to raise productivity in FPGA functional debug. | Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le |
| 2009 | DATE | Automated data analysis solutions to silicon debug. | Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris |
| 2009 | DATE | Sequential logic rectifications with approximate SPFDs. | Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith |
| 2008 | IOLTS | On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. | Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris |
| 2007 | ASPDAC | Automating Logic Rectification by Approximate SPFDs. | Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton |
| 2006 | ITC | Seamless Integration of SER in Rewiring-Based Design Space Exploration. | Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris |
| 2005 | DATE | Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. | Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman |
| 2003 | ITC | Extraction Error Diagnosis and Correction in High-Performance Designs. | Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris |