Yu-Tsun Chien
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
1999–2005
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | DATE | Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. | Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee |
| 2000 | ISCAS | Design of an inter-plane circuit for clocked PLAs. | Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen |
| 1999 | ISCAS | A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. | Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen |