Yuan-Kai Ho
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2008–2013
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ASPDAC | Layer minimization in escape routing for staggered-pin-array PCBs. | Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng |
| 2013 | DAC | Multiple chip planning for chip-interposer codesign. | Yuan-Kai Ho, Yao-Wen Chang |
| 2012 | DAC | Obstacle-avoiding free-assignment routing for flip-chip designs. | Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen |
| 2011 | ICCAD | Escape routing for staggered-pin-array PCBs. | Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang |
| 2010 | ASPDAC | Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. | Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang |
| 2008 | DAC | Type-matching clock tree for zero skew clock gating. | Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu |