| 2020 | ITC | High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips. | Zeye Liu, R. D. Shawn Blanton |
| 2019 | CVPR | Regularizing Activation Distribution for Training Binarized Deep Networks. | Ruizhou Ding, Ting-Wu Chin, Zeye Liu, Diana Marculescu |
| 2019 | DAC | FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. | Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, R. D. (Shawn) Blanton |
| 2019 | ICCD | IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design. | Qicheng Huang, Chenlei Fang, Zeye Liu, Ruizhou Ding, R. D. Shawn Blanton |
| 2019 | ITC | Improving Test Chip Design Efficiency via Machine Learning. | Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton |
| 2019 | VTS | Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle. | Ben Niewenhuis, Balaji Ravikumar, Zeye Liu, R. D. Shawn Blanton |
| 2018 | ASPDAC | Quantized deep neural networks for energy efficient hardware-based inference. | Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu |
| 2018 | ICCD | Back-End Layout Reflection for Test Chip Design. | Zeye Liu, Ronald D. Blanton |
| 2017 | ITC | Front-end layout reflection for test chip design. | Zeye Liu, Phillip Fynan, Ronald D. Blanton |
| 2016 | DATE | Achieving 100% cell-aware coverage by design. | Zeye Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton |
| 2016 | ITC | Logic characterization vehicle design reflection via layout rewiring. | Phillip Fynan, Zeye Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton |
| 2016 | ITC | Test chip design for optimal cell-aware diagnosability. | Soumya Mittal, Zeye Liu, Ben Niewenhuis, R. D. (Shawn) Blanton |