Zhipei Chi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
2
Active years
1999–2002
Best venue rank
Multiconference
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2002 | ICASSP | High speed algorithm and VLSI architecture design for decoding BCH product codes. | Zhipei Chi, Keshab K. Parhi |
| 2002 | ISCAS | High speed VLSI architecture design for block turbo decoder. | Zhipei Chi, Keshab K. Parhi |
| 2001 | ICASSP | A study on the performance, power consumption tradeoffs of short frame turbo decoder design. | Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi |
| 2001 | ICASSP | Area-efficient high speed decoding schemes for turbo/MAP decoders. | Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi |
| 2001 | ISCAS | A study on the performance, complexity tradeoffs of block turbo decoder design. | Zhipei Chi, Leilei Song, Keshab K. Parhi |
| 2000 | ICASSP | High throughput low energy FEC/ARQ technique for short frame turbo codes. | Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi |
| 1999 | ISCAS | Pipelined QR decomposition based multi-channel least square lattice adaptive filter architectures. | Zhipei Chi, Jun Ma, Keshab K. Parhi |