Zhiqiang Cui
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
1
Active years
2006–2014
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | ISCAS | Multilevel error correction scheme for MLC flash memory. | Zhiqiang Cui, Zhongfeng Wang, Xinming Huang |
| 2009 | ISCAS | Towards an Optimal Trade-off of Viterbi Decoder Design. | Jinjin He, Zhongfeng Wang, Zhiqiang Cui, Li Li |
| 2007 | ISCAS | Efficient Message Passing Architecture for High Throughput LDPC Decoder. | Zhiqiang Cui, Zhongfeng Wang |
| 2006 | ISCAS | A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. | Zhiqiang Cui, Zhongfeng Wang |
| 2006 | ISCAS | Area-efficient parallel decoder architecture for high rate QC-LDPC codes. | Zhiqiang Cui, Zhongfeng Wang |