| 2026 | ASPDAC | Spiking-NeRF: Neural Graphics Acceleration With Spiking Feature Encoding for Edge 3D Rendering. | Jianzhen Gao, Wei Liu, Yue Liu, Hengyi Zhou, Zhiyi Yu, Shanlin Xiao |
| 2026 | ASPDAC | An Algorithm-Hardware Co-Design for Efficient and Robust Spiking Neural Networks via Sparsity. | Wei Liu, Yinsheng Chen, Jilong Luo, Yusa Wang, Zhiyi Yu, Shanlin Xiao |
| 2026 | ASPDAC | NBCache: An Efficient and Scalable Non-Blocking Cache for Coherent Multi-Chiplet Systems. | Zhirong Ye, Yongchang Zhang, Peilin Wang, Tao Lu, Zhaolin Li, Zhiyi Yu, Mingyu Wang |
| 2026 | HPCA | LRM-GPU: Alleviating Synchronization Overhead for Multi-Chiplet GPU Architecture. | Baiqing Zhong, Zhirong Ye, Xiaojie Li, Peilin Wang, Haiqiu Huang, Zhaolin Li, Zhiyi Yu, Mingyu Wang |
| 2025 | ASPDAC | SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural Networks. | Bo Li, Yue Liu, Wei Liu, Jinghai Wang, Xiao Huang, Zhiyi Yu, Shanlin Xiao |
| 2025 | DAC | Towards In-Situ Neuromorphic Computing Architecture for Event Stream Super-Resolution. | Yihe Yu, Bo Li, Kexin Huang, Wei Liu, Jinghai Wang, Yue Liu, Zhiyi Yu, Shanlin Xiao |
| 2025 | DATE | FDAIMC: A Fully-Differential Analog In-Memory-Computing for MAC in MRAM with Accuracy Calibration Under Process and Voltage Variation. | Xiangyu Li, Weichong Chen, Ruida Hong, Jinghai Wang, Ningyuan Yin, Zhiyi Yu |
| 2025 | DATE | A Low-Complexity True Random Number Generation Scheme Using 3D-NAND Flash Memory. | Ruibin Zhou, Jian Huang, Xianping Liu, Yuhan Wang, Xinrui Zhang, Yungen Peng, Zhiyi Yu |
| 2025 | MICRO | C3ache: Towards Hierarchical Cache-Centric Computing for Sparse Matrix Multiplication on GPGPUs. | Xiaojie Li, Mingyu Wang, Baiqing Zhong, Haiqiu Huang, Guangjie Cao, Zhiyi Yu |
| 2024 | DATE | An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint. | Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu |
| 2024 | ICASSP | Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer. | Yue Liu, Shanlin Xiao, Bo Li, Zhiyi Yu |
| 2024 | ICCD | CCacheSim: A Circuit-Architecture Cross-Level Simulation Framework for SRAM-Based in-Cache Computing System Evaluation. | Baiqing Zhong, Mingyu Wang, Yicong Zhang, Xiaojie Li, Zhiyi Yu |
| 2024 | MICRO | Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations. | Yicong Zhang, Mingyu Wang, Wangguang Wang, Yangzhan Mai, Haiqiu Huang, Zhiyi Yu |
| 2023 | ICA3PP | CRAFT: Common Router Architecture for Throughput Optimization. | Jiahua Yan, Mingyu Wang, Yao Qin, Zhiyi Yu |
| 2023 | ICPADS | LWSDP: Locality-Aware Warp Scheduling and Dynamic Data Prefetching Co-design in the Per-SM Private Cache of GPGPUs. | Wangguang Wang, Mingyu Wang, Yicong Zhang, Yukun Wei, Zhiyi Yu |
| 2023 | ICPADS | A Scalable Deadlock-Free Static Routing Algorithm for Chiplet-Based Systems. | Xiaoran Zhang, Mingyu Wang, Yicong Zhang, Tao Lu, Zhiyi Yu |
| 2023 | ISCAS | A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips. | Yangzhan Mai, Mingyu Wang, Chuanghao Zhang, Baiqing Zhong, Zhiyi Yu |
| 2021 | FCCM | 3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA. | Huipeng Deng, Jian Wang, Huafeng Ye, Shanlin Xiao, Xiangyu Meng, Zhiyi Yu |
| 2020 | ICPR | SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs. | Xingyu Yang, Mingyuan Meng, Shanlin Xiao, Zhiyi Yu |
| 2020 | IJCNN | Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks. | Mingyuan Meng, Xingyu Yang, Shanlin Xiao, Zhiyi Yu |
| 2020 | ISCAS | A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection. | Wenkang Liao, Yuhao Guo, Shanlin Xiao, Zhiyi Yu |
| 2018 | ISCAS | An Automatic Task Partition Method for Multi-core System. | Ming-e Jing, Yujie Huang, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng, Zhiyi Yu |
| 2013 | ISCAS | Implementation and optimization of 3780-point FFT on multi-core system. | Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Jiayi Sheng, Haofan Yang |
| 2013 | ISCAS | Time-Division-Multiplexer based routing algorithm for NoC system. | Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Liyang Zhou |
| 2013 | ISCAS | A low power register file with asynchronously controlled read-isolation and software-directed write-discarding. | Zheng Yu, Jiajie Zhang, Xueqiu Yu, Xiaoyang Zeng, Zhiyi Yu |
| 2012 | ISCAS | Evaluating performance of manycore processors with various granularities considering yield and lifetime reliability. | Yueming Yang, Zewen Shi, Jianming Yu, Liulin Zhong, Xiaoyang Zeng, Zhiyi Yu |
| 2012 | ISCAS | A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost. | Yan Ying, Kaidi You, Liyang Zhou, Heng Quan, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng |
| 2012 | ISCAS | Task-binding based branch-and-bound algorithm for NoC mapping. | Liyang Zhou, Ming-e Jing, Liulin Zhong, Zhiyi Yu, Xiaoyang Zeng |
| 2011 | ISCAS | A reconfigurable and deadlock-free routing algorithm for 2D Mesh Network-on-Chip. | Zewen Shi, Yueming Yang, Xiaoyang Zeng, Zhiyi Yu |
| 2011 | ISCAS | Fault tolerant computing for stream DSP applications using GALS multi-core processors. | Zhiyi Yu, Zewen Shi, Xiaoyang Zeng |
| 2010 | ISCAS | A scalable and fault-tolerant routing algorithm for NoCs. | Zewen Shi, Kaidi You, Yan Ying, Bei Huang, Xiaoyang Zeng, Zhiyi Yu |
| 2008 | ISCAS | A low-area interconnect architecture for chip multiprocessors. | Zhiyi Yu, Bevan M. Baas |
| 2006 | ICCD | Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. | Zhiyi Yu, Bevan M. Baas |