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Formal Methods in Computer-Aided Design

FMCAD

B

CORE rank

CORE rank (raw)

B

Fields of research

Software Engineering

Papers indexed

840

1996–2025

Papers per year

199645 peak2025

FMCAD papers

840 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2013On the concept of variable roles and its use in software analysis.Yulia Demyanova, Helmut Veith, Florian Zuleger
2013Computing prime implicants.David Dharbe, Pascal Fontaine, Daniel Le Berre, Bertrand Mazure
2013Invariants for finite instances and beyond.Sylvain Conchon, Amit Goel, Sava Krstic, Alain Mebsout, Fatiha Zadi
2013Using process modeling and analysis techniques to reduce errors in healthcare.Lori A. Clarke
2013A circuit approach to LTL model checking.Koen Claessen, Niklas En, Baruch Sterin
2013Parameter synthesis with IC3.Alessandro Cimatti, Alberto Griggio, Sergio Mover, Stefano Tonetta
2013Distributed synthesis for LTL fragments.Krishnendu Chatterjee, Thomas A. Henzinger, Jan Otop, Andreas Pavlogiannis
2013Verifying periodic programs with priority inheritance locks.Sagar Chaki, Arie Gurfinkel, Ofer Strichman
2013Efficient modular SAT solving for IC3.Sam Bayless, Celina G. Val, Thomas Ball, Holger H. Hoos, Alan J. Hu
2013Static verification based signoff - A key enabler for managing verification complexity in the modern soc.Pranav Ashar
2013Counter-strategy guided refinement of GR(1) temporal logic specifications.Rajeev Alur, Salar Moarref, Ufuk Topcu
2013Syntax-guided synthesis.Rajeev Alur, Rastislav Bodk, Garvit Juniwal, Milo M. K. Martin, Mukund Raghothaman, Sanjit A. Seshia, Rishabh Singh, Armando Solar-Lezama, Emina Torlak, Abhishek Udupa
2013Generalized counterexamples to liveness properties.Gadi Aleksandrowicz, Jason Baumgartner, Alexander Ivrii, Ziv Nevo
2012Piecewise linear modeling of nonlinear devices for formal verification of analog circuits.Yan Zhang, Sriram Sankaranarayanan, Fabio Somenzi
2012Forward and backward: Bounded model checking of linear hybrid automata from two directions.Yang Yang, Lei Bu, Xuandong Li
2012Oscillator verification with probability one.Chao Yan, Mark R. Greenstreet
2012Enhanced reachability analysis via automated dynamic netlist-based hint generation.Jiazhao Xu, Mark Williams, Hari Mony, Jason Baumgartner
2012Lazy abstraction and SAT-based reachability in hardware model checking.Yakir Vizel, Orna Grumberg, Sharon Shoham
2012Formal for everyone - Challenges in achievable multicore design and verification.Daryl Stewart
2012Verification with small and short worlds.Rohit Sinha, Cynthia Sturton, Petros Maniatis, Sanjit A. Seshia, David A. Wagner
2012Efficient predictive analysis for detecting nondeterminism in multi-threaded programs.Arnab Sinha, Sharad Malik, Aarti Gupta
2012Incremental upgrade checking by means of interpolation-based function summaries.Ondrej Sery, Grigory Fedyukovich, Natasha Sharygina
2012Answer Set Programming.Torsten Schaub
2012Decompilation into logic - Improved.Magnus O. Myreen, Michael J. C. Gordon, Konrad Slind
2012Formal verification of error correcting circuits using computational algebraic geometry.Alexey Lvov, Luis Alfonso Lastras-Montao, Viresh Paruthi, Robert Shadowen, Ali El-Zein
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