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Paper
A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuit.
Yasuhiro Sugimoto
,
Tetsuya Iida
Venue
B
ASPDAC
Year
1997
Proceedings
ASP-DAC
DBLP record
conf/aspdac/SugimotoI97 ↗
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