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Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs.
Mrio P. Vstias
,
Horcio C. Neto
,
Helena Sarmento
Venue
C
DSD
Year
2012
Proceedings
DSD
DBLP record
conf/dsd/VestiasNS12 ↗
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