| 2024 | ARITH | PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. | Jos T. de Sousa, Joo D. Lopes, Micaela Serdio, Horcio C. Neto, Mrio P. Vstias |
| 2019 | FPL | Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. | Mrio P. Vstias, Rui Policarpo Duarte, Jos T. de Sousa, Horcio C. Neto |
| 2019 | ISCAS | Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. | Lus Fiolhais, Fernando M. Gonalves, Rui Policarpo Duarte, Mrio P. Vstias, Jos T. de Sousa |
| 2018 | FPL | Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. | Mrio P. Vstias, Rui Policarpo Duarte, Jos T. de Sousa, Horcio C. Neto |
| 2017 | FPL | K-means clustering on CGRA. | Joo D. Lopes, Jos T. de Sousa, Horcio C. Neto, Mrio P. Vstias |
| 2017 | FPL | Parallel dot-products for deep learning on FPGA. | Mrio P. Vstias, Rui Policarpo Duarte, Jos T. de Sousa, Horcio C. Neto |
| 2016 | FPL | Multi-core for K-means clustering on FPGA. | Jose Canilho, Mrio P. Vstias, Horcio C. Neto |
| 2015 | DSD | Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture. | Joo Pinho, Wilson Jos, Horcio C. Neto, Mrio P. Vstias |
| 2015 | DSD | Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA. | Tiago Rodrigues, Mrio P. Vstias |
| 2015 | FPL | Enhancing stochastic computations via process variation. | Rui Policarpo Duarte, Mrio P. Vstias, Horcio C. Neto |
| 2015 | IGARSS | FPGA-based architecture for hyperspectral unmixing. | Jos M. P. Nascimento, Mrio P. Vstias, Gabriel Martn |
| 2014 | FPL | Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. | Wilson Jos, Ana Rita Silva, Horcio C. Neto, Mrio P. Vstias |
| 2014 | FPL | Trends of CPU, GPU and FPGA for high-performance computing. | Mrio P. Vstias, Horcio C. Neto |
| 2013 | FPL | Analysis of matrix multiplication on high density Virtex-7 FPGA. | Wilson Jos, Ana Rita Silva, Horcio C. Neto, Mrio P. Vstias |
| 2013 | FPL | A reconfigurable computing architecture using magnetic tunneling junction memories. | Victor Silva, Jorge R. Fernandes, Mrio P. Vstias, Horcio C. Neto |
| 2012 | DSD | Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm. | Mrio P. Vstias, Horcio C. Neto |
| 2012 | DSD | Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs. | Mrio P. Vstias, Horcio C. Neto, Helena Sarmento |
| 2012 | FPL | Sliding block Viterbi decoders in FPGA. | Mrio P. Vstias, Horcio C. Neto, Helena Sarmento |
| 2011 | FPL | Revisiting the Newton-Raphson Iterative Method for Decimal Division. | Mrio P. Vstias, Horcio C. Neto |
| 2009 | DSD | Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. | Rui Policarpo Duarte, Horcio C. Neto, Mrio P. Vstias |
| 2009 | DSD | Run-Time Reconfigurable Array Using Magnetic RAM. | Victor Silva, Lus Bica Oliveira, Jorge R. Fernandes, Mrio P. Vstias, Horcio C. Neto |
| 2008 | FPL | Decimal multiplier on FPGA using embedded binary multipliers. | Horcio C. Neto, Mrio P. Vstias |
| 2007 | FPL | Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. | Mrio P. Vstias, Horcio C. Neto |
| 2006 | ASPDAC | Co-synthesis of a configurable SoC platform based on a network on chip architecture. | Mrio P. Vstias, Horcio C. Neto |
| 2006 | FPL | A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. | Mrio P. Vstias, Horcio C. Neto |
| 2002 | RSP | System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures. | Mrio P. Vstias, Horcio C. Neto |