On the IC architecture and design of a 2 m CMOS 8 MIPS digital signal processor with parallel processing capability: The PCB5010/5011.

Frans J. van Wijk, Frank P. Welten, Jef L. van Meerbergen, Jan Stoter, Jos A. Huisken, Antoine Delaruelle, Karel E. van Eerdewijk, Josef Schmid, Jan H. Wittek

Browse the full ICASSP paper archive.