A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers.
Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita
VenueAICS
Year1993
ProceedingsInternational Conference on Supercomputing
DBLP recordconf/ics/NakamuraBWININY93 ↗
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