A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators : - Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation -.

Quan Cheng, Huizi Zhang, Qiufeng Li, Yuan Liang, Mingtao Zhang, Zhenzhe Chen, Ruilin Zhang, Jinjun Xiong, Mingqiang Huang, Longyang Lin, Masanori Hashimoto

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