| 2026 | ASPDAC | Gundam: A Generalized Unified Design and Analysis Model for Matrix Multiplication on Edge. | Quan Cheng, Haoyuan Li, Weirong Dong, Mingqiang Huang, Longyang Lin, Masanori Hashimoto |
| 2026 | ASPDAC | FIawase: A SET Fault Injection Framework Towards Exhaustive System-Level Impact Evaluation. | Mingtao Zhang, Quan Cheng, Masanori Hashimoto |
| 2026 | DATE | Ramen: Radiation-Aware Modeling Framework for PDK-Enabled Design and Library Characterization. | Quan Cheng, Haoyuan Li, Zhenzhe Chen, Wang Liao, Jing-Jia Liou, Masanori Hashimoto, Longyang Lin |
| 2026 | DATE | Gohan: A Golden-Copy-Aided Platform Enabling Online Hybrid-Interactive Reliability Analysis. | Quan Cheng, Haoyuan Li, Wang Liao, Feng Liang, Longyang Lin, Masanori Hashimoto |
| 2025 | ASPDAC | ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges. | Masanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi |
| 2025 | ASPDAC | Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications. | Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto |
| 2025 | DATE | HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation. | Quan Cheng, Wang Liao, Ruilin Zhang, Hao Yu, Longyang Lin, Masanori Hashimoto |
| 2025 | ICCAD | Tenpura: A General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-fast Reliability Analysis. | Quan Cheng, Huizi Zhang, Chien-Hsing Liang, Mingtao Zhang, Jing-Jia Liou, Jinjun Xiong, Longyang Lin, Masanori Hashimoto |
| 2025 | ISLPED | A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators : - Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation -. | Quan Cheng, Huizi Zhang, Qiufeng Li, Yuan Liang, Mingtao Zhang, Zhenzhe Chen, Ruilin Zhang, Jinjun Xiong, Mingqiang Huang, Longyang Lin, Masanori Hashimoto |
| 2025 | ITC | Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis. | Quan Cheng, Hao-Yang Chi, Chien-Hsing Liang, Yu-Hong Chao, Huizi Zhang, Yuan Liang, Mingtao Zhang, Wang Liao, Jinjun Xiong, Jing-Jia Liou, Masanori Hashimoto, Longyang Lin |
| 2025 | SiggraphA | High-Clarity Underwater 3D Display Enabled by Electrolysis-Free Water-Mediated Wireless Power Transmission. | Chiaki Takahashi, Hayato Sawada, Ryo Shirai, Masanori Hashimoto |
| 2024 | ASPDAC | Logic Locking over TFHE for Securing User Data and Algorithms. | Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto |
| 2024 | DAC | How accurately can soft error impact be estimated in black-box/white-box cases? - a case study with an edge AI SoC -. | Quan Cheng, Qiufeng Li, Longyang Lin, Wang Liao, Liuyao Dai, Hao Yu, Masanori Hashimoto |
| 2024 | ICCD | S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators. | Mingtao Zhang, Quan Cheng, Hiromitsu Awano, Longyang Lin, Masanori Hashimoto |
| 2024 | SiggraphA | Development of Tiny Wireless Position Tracker Enabling Real-Time Intuitive 3D Modeling. | Yuki Maegawa, Masanori Hashimoto, Ryo Shirai |
| 2023 | IOLTS | Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication. | Riku Iwamoto, Masanori Hashimoto |
| 2023 | IUI | Toward Instant 3D Modeling: Highly Parallelizable Shape Reproduction Method for Soft Object Containing Numerous Tiny Position Trackers. | Minoru Harimaya, Ryo Shirai, Masanori Hashimoto |
| 2022 | DATE | Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections. | Yangchao Zhang, Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Masanori Hashimoto |
| 2022 | IUI | Shape-Flexible Underwater Display System with Wirelessly Powered and Controlled Smart LEDs. | Ryo Shirai, Masanori Hashimoto |
| 2021 | ASPDAC | Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization. | TaiYu Cheng, Yukata Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto |
| 2021 | BMVC | Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. | ngel Lpez Garca-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu |
| 2021 | DATE | MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. | Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi |
| 2021 | DATE | BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter. | Dehua Liang, Masanori Hashimoto, Hiromitsu Awano |
| 2021 | DATE | Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. | Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto |
| 2021 | ISCAS | Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling. | TaiYu Cheng, Masanori Hashimoto |
| 2021 | SiggraphA | Submarine LED: Wirelessly powered underwater display controlling its buoyancy. | Ryo Shirai, Masanori Hashimoto |
| 2020 | ASPDAC | Soft Error and Its Countermeasures in Terrestrial Environment. | Masanori Hashimoto, Wang Liao |
| 2020 | ASPDAC | When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. | Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo |
| 2020 | DATE | BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA. | Hiromitsu Awano, Masanori Hashimoto |
| 2020 | DATE | Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA. | Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto |
| 2020 | ISCAS | Low-Cost Reservoir Computing using Cellular Automata and Random Forests. | ngel Lpez Garca-Arias, Jaehoon Yu, Masanori Hashimoto |
| 2020 | ITC | Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction. | Jun Chen, Masanori Hashimoto |
| 2020 | ITC | Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing. | Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Kojiro Ito, Masanori Hashimoto |
| 2019 | IUI | Coverage-scalable instant tabletop positioning system with self-localizable anchor nodes. | Pei Hao Chen, Ryo Shirai, Masanori Hashimoto |
| 2018 | ASPDAC | MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits. | Yutaka Masuda, Masanori Hashimoto |
| 2018 | DAC | Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. | Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann |
| 2018 | ICCAD | Sneak path free reconfiguration of via-switch crossbars based FPGA. | Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto |
| 2018 | ICCAD | Comparing voltage adaptation performance between replica and in-situ timing monitors. | Yutaka Masuda, Jun Nagayama, Hirotaka Takeno, Yoshimasa Ogawa, Yoichi Momiyama, Masanori Hashimoto |
| 2017 | ISCAS | Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node. | Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto |
| 2017 | IUI | GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction. | Kauzki Hirosue, Shohei Ukawa, Yuichi Itoh, Takao Onoye, Masanori Hashimoto |
| 2016 | ASPDAC | Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. | Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li |
| 2016 | FPL | A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. | Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto |
| 2016 | ICCAD | Critical path isolation for time-to-failure extension and lower voltage operation. | Yutaka Masuda, Masanori Hashimoto, Takao Onoye |
| 2016 | IOLTS | Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms. | Yutaka Masuda, Masanori Hashimoto, Takao Onoye |
| 2015 | ASPDAC | An oscillator-based true random number generator with process and temperature tolerance. | Takehiko Amaki, Masanori Hashimoto, Takao Onoye |
| 2015 | ASPDAC | Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. | Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera |
| 2015 | ASPDAC | Area efficient device-parameter estimation using sensitivity-configurable ring oscillator. | Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye |
| 2015 | ICCAD | Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise. | Yutaka Masuda, Masanori Hashimoto, Takao Onoye |
| 2015 | IOLTS | Real-time on-chip supply voltage sensor and its application to trace-based timing error localization. | Miho Ueno, Masanori Hashimoto, Takao Onoye |
| 2015 | ITC | Stochastic timing error rate estimation under process and temporal variations. | Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye |
| 2015 | VR | 3D node localization from node-to-node distance information using cross-entropy method. | Shohei Ukawa, Tatsuya Shinada, Masanori Hashimoto, Yuichi Itoh, Takao Onoye |
| 2013 | ETS | Extracting device-parameter variations using a single sensitivity-configurable ring oscillator. | Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif |
| 2013 | ICCAD | Stochastic error rate estimation for adaptive speed control with field delay testing. | Shoichi Iizuka, Masafumi Mizuno, Dan Kuroda, Masanori Hashimoto, Takao Onoye |
| 2012 | ASPDAC | Body bias clustering for low test-cost post-silicon tuning. | Shuta Kimura, Masanori Hashimoto, Takao Onoye |
| 2012 | FPL | A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. | Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye |
| 2011 | ASPDAC | Jitter amplifier for oscillator-based true random number generator. | Takehiko Amaki, Masanori Hashimoto, Takao Onoye |
| 2011 | ASPDAC | Run-time adaptive performance compensation using on-chip sensors. | Masanori Hashimoto |
| 2011 | ASPDAC | Device-parameter estimation with on-chip variation sensors considering random variability. | Kenichi Shinkai, Masanori Hashimoto |
| 2011 | FPL | Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures. | Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye |
| 2011 | ISCAS | An oscillator-based true random number generator with jitter amplifier. | Takehiko Amaki, Masanori Hashimoto, Takao Onoye |
| 2010 | ASPDAC | Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2010 | ASPDAC | Gate delay estimation in STA under dynamic power supply noise. | Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto |
| 2010 | WISA | A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. | Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2009 | ASPDAC | Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2009 | ASPDAC | High performance on-chip differential signaling using passive compensation for global communication. | Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng |
| 2009 | FPL | Coarse-grained dynamically reconfigurable architecture with flexible reliability. | Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye |
| 2009 | ISLPED | Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. | Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2008 | ASPDAC | Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. | Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye |
| 2008 | ASPDAC | High performance current-mode differential logic. | Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto |
| 2008 | ICCAD | Decoupling capacitance allocation for timing with statistical noise model and timing analysis. | Takashi Enami, Masanori Hashimoto, Takashi Sato |
| 2008 | ICCD | On-chip high performance signaling using passive compensation. | Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng |
| 2008 | ISLPED | Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2006 | ASPDAC | Interconnect RL extraction at a single representative frequency. | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
| 2006 | ICCAD | A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. | Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye |
| 2006 | ICCD | Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. | Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye |
| 2005 | ASPDAC | Timing analysis considering temporal supply voltage fluctuation. | Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera |
| 2005 | ASPDAC | Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. | Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera |
| 2005 | ASPDAC | On-chip thermal gradient analysis and temperature flattening for SoC design. | Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto |
| 2005 | ASPDAC | Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18m CMOS process. | Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera |
| 2005 | ASPDAC | Return path selection for loop RL extraction. | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
| 2004 | ASPDAC | A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. | Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera |
| 2004 | ASPDAC | Representative frequency for interconnect R(f)L(f)C extraction. | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
| 2004 | ICCAD | Timing analysis considering spatial power/ground level variation. | Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera |
| 2003 | ASPDAC | Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies. | Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera |
| 2003 | ASPDAC | Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. | Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto |
| 2003 | ICCAD | Equivalent Waveform Propagation for Static Timing Analysis. | Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera |
| 2001 | ASPDAC | Post-layout transistor sizing for power reduction in cell-based design. | Masanori Hashimoto, Hidetoshi Onodera |
| 2001 | ICCD | Crosstalk Noise Estimation for Generic RC Trees. | Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera |
| 2001 | ISCAS | Increase in delay uncertainty by performance optimization. | Masanori Hashimoto, Hidetoshi Onodeva |
| 1999 | DAC | A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru |
| 1998 | ISLPED | A power optimization method considering glitch reduction by gate sizing. | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru |