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Paper
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches.
Maryam Shojaei Baghini
,
Madhav P. Desai
Venue
National
VLSID
Year
2002
Proceedings
ASP-DAC/VLSI Design
DBLP record
conf/vlsid/BaghiniD02 ↗
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