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Madhav P. Desai

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

28

Venues

9

Active years

1996–2024

Best venue rank

A*

Where they publish

Papers

28 indexed papers, newest first.

YearVenueTitleAuthors
2024WSCEfficient Parallel Simulation of Networked Synchronous Discrete-Event Systems.Neha V. Karanjkar, Madhav P. Desai, Akhil Kushe, Anish Natekar
2022SIMULTECHSitar: A Cycle-based Discrete-Event Simulation Framework for Architecture Exploration.Neha V. Karanjkar, Madhav P. Desai
2015DSDA Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients.Nanditha P. Rao, Madhav P. Desai
2015MASCOTSAn Approach to Discrete Parameter Design Space Exploration of Multi-core Systems Using a Novel Simulation Based Interpolation Technique.Neha V. Karanjkar, Madhav P. Desai
2012USENIXThe Click2NetFPGA Toolchain.Teemu Rinta-aho, Mika Karlstedt, Madhav P. Desai
2010DSDA C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems.Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai
2010VLSIDBottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems.Gautam Hazari, Madhav P. Desai, G. Srinivas
2009MASCOTSLearning based address mapping for improving the performance of memory subsystems.Pratyush Kumar, Madhav P. Desai
2007VLSIDOn the Impact of Address Space Assignment on Performance in Systems-on-Chip.Gautam Hazari, Madhav P. Desai, H. Kasture
2007VLSIDAHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs.Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai
2007VLSIDParallelization of DC Analysis through Multiport Decomposition.Gaurav Trivedi, Madhav P. Desai, H. Narayanan
2006VLSIDFast DC Analysis and Its Application to Combinatorial Optimization Problems.Gaurav Trivedi, Madhav P. Desai, H. Narayanan
2005VLSIDVariance Reduction in Monte Carlo Capacitance Extraction.Shabbir H. Batterywala, Madhav P. Desai
2005WiOptOn Range Matrices and Wireless Networks in d Dimensions.Madhav P. Desai, D. Manjunath
2004VLSIDA Novel Technique Towards Eliminating the Global Clock in VLSI Circuits.Gautam Hazari, Madhav P. Desai, Apoorv Gupta, Supratik Chakraborty
2004VLSIDA Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator.Aditya Mittal, Madhav P. Desai
2004VLSIDOn Buffering Schemes for Long Multi-Layer Nets.Vani Prasad, Madhav P. Desai
2003VLSIDDetailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics.Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao
2003VLSIDInterconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy.Vani Prasad, Madhav P. Desai
2002VLSIDImpact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches.Maryam Shojaei Baghini, Madhav P. Desai
2001VLSIDEffect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao
2001VLSIDAn On-Chip Coupling Capacitance Measurement Technique.Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai
2000VLSIDInductance Characterization of Small Interconnects Using Test-Signal Method.Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal
1999ICCDDecomposition of Finite State Machines for Area, Delay Minimization.Rupesh S. Shelar, Madhav P. Desai, H. Narayanan
1999VLSIDA State Assignment Scheme Targeting Performance and Area.B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai
1998DACRobust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor.Nevine Nassif, Madhav P. Desai, Dale H. Hall
1996DACSizing of Clock Distribution Networks for High Performance CPU Chips.Madhav P. Desai, Radenko Cvijetic, James Jensen
1996DACA Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation.Madhav P. Desai, Yao-Tsung Yen